MEMORY WRITE MANAGEMENT IN A COMPUTER SYSTEM

摘要

In accordance with the present description, an apparatus for use with a source issuing write operations to a target, wherein the device includes an I/O port, and logic of the target configured to detect a flag issued by the source in association with the issuance of a first plurality of write operations. In response to detection of the flag, the logic of the target ensures that the first plurality of write operations are completed in a memory prior to completion of any of the write operations of the second plurality of write operations. Also described is an apparatus of the source which includes an I/O port, and logic of the source configured to issue the first plurality of write operations and to issue a write fence flag in association with the issuance of a first plurality of write operations. Other aspects are described herein.

主权项

1. An apparatus of a source for use with a target receiving write operations for a memory of the target, comprising:
an input/output (I/O) port; and a data transfer accelerator having source logic of the source configured to:
issue to the I/O port, a first plurality of write operations to write data in the target memory, a write fence flag associated with the first plurality of write operations, and a second plurality of write operations to write data in the target memory; wherein the write fence flag is configured by the source logic for detection by the target to ensure that the first plurality of write operations are completed by the target in the target memory prior to completion of any of the write operations of the second plurality of write operations.