| 主权项 |
1. A NAND memory chip configured for pipeline/concurrent All-BL (ABL) SLC program without program-verify and ABL-like SLC read operations, the NAND memory chip comprising:
a NAND array comprising J numbers of HG groups arranged in a bitline (BL) direction, each HG group including L numbers of MG groups, each MG group including J′ numbers of LG groups, each LG group including H numbers of blocks, each block including N numbers of strings cascaded one another in a wordline (WL) direction orthogonal to the BL-direction, each string comprising K numbers of NAND memory cells capped by a pair of string-select transistors respectively at two ends of the string having its source node connected to a common source line laid in the WL-direction, wherein N, J, L, J′, H, and K are integers of 2 and greater based on memory chip design; a two-level BL hierarchical structure comprising N/2 first metal lines laid at a first level as global bit lines (GBLs) in the BL-direction through the NAND array and broken by J−1 rows of N/2 GBL-dividers forming a set of N/2 broken-GBLs associated with one of J HG groups, and comprising N second metal lines laid below the first level as local bit lines (LBLs) in the BL-direction through each MG group forming one page of N-bit on-chip capacitors CMGs, each pair of Odd and Even LBLs being connected to one GBL via a 2-to-1 MG-Ypass device, each of the N LBLs being divided to J′ pages of N broken-LBLs by J′−1 rows of N LBL-dividers, each page of N broken-LBLs being associated with a LG group as one page of N-bit parasitic capacitors CLGs and respectively connecting to drain nodes of N strings of each block of the LG group wherein N/2 Odd-numbered broken-LBLs and N/2 Even-numbered broken-LBLs are commonly connected to a precharge power line respectively via N/2 Odd-precharger devices and N/2 Even-precharger devices for charging a medium-high voltage Vinh of about 7V or lower or discharging to ground or other small voltages; a plurality of group-decoders including BHG-DEC, MG-DEC, BLG-DEC, and LG-based precharge power line decoder for providing respective gate control signals; a row-decoder control circuit including a plurality of LG-based row-decoders, each LG-based row-decoder including a time control unit and H block-decoders, each block-decoder being configured to provide line control signals for K WLs of NAND cells and a pair of gate lines of string-select transistors per block; a peripheral system comprising a data communication group and a command control group, the data communication group including a N/2-bit page buffer circuit coupled between the N/2 GBLs and I/Os for program data loading and read data sensing, the command control group including a command interface, a state-machine circuit, an address register circuit, and a voltage generator for receiving/transmitting external control signals, controlling I/Os to operate the page buffer operated with a low Vdd operating voltage, and generating various required high, medium, and analog low voltages and address information for the row-decoder control circuit and the plurality of group-decoders to set desired bias conditions for performing multi-WLs pipeline/concurrent ABL SLC program without program-verify and ABL-like read operation with substantial reduction in operation latency. |
