发明名称 |
VOLTAGE LEVEL SHIFTED SELF-CLOCKED WRITE ASSISTANCE |
摘要 |
Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals. |
申请公布号 |
WO2016048660(A1) |
申请公布日期 |
2016.03.31 |
申请号 |
WO2015US49220 |
申请日期 |
2015.09.09 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
HOFF, DAVID PAUL;KULKARNI, AMEY;MARTZLOFF, JASON PHILIP;LILES, STEPHEN EDWARD |
分类号 |
G11C11/419;G11C5/14;G11C7/10;G11C7/12;H03K19/017 |
主分类号 |
G11C11/419 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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