发明名称 |
HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR INTEGRATED INTO EXTREMELY THIN SEMICONDUCTOR ON INSULATOR PROCESS |
摘要 |
An electrical device including a first semiconductor device in a first region of the SOI substrate and a second semiconductor device is present in a second region of the SOI substrate. The first semiconductor device comprises a first source and drain region that is present in the SOI layer of the SOI substrate, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer. The second semiconductor device comprises a second source and drain region present in a base semiconductor layer of the SOI substrate and a second gate structure, wherein a gate dielectric of the second gate structure is provided by a buried dielectric layer of the SOI substrate and a gate conductor of the second gate structure comprises a same material as the raised source and drain region. |
申请公布号 |
US2016093638(A1) |
申请公布日期 |
2016.03.31 |
申请号 |
US201514958171 |
申请日期 |
2015.12.03 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
Cheng Kangguo;Doris Bruce B.;Khakifirooz Ali;Shahidi Ghavam G. |
分类号 |
H01L27/12;H01L21/265;H01L21/3213;H01L29/06;H01L29/08;H01L29/417;H01L29/423;H01L21/84;H01L29/10 |
主分类号 |
H01L27/12 |
代理机构 |
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代理人 |
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主权项 |
1. A method of forming a semiconductor device comprising:
forming a first semiconductor device in the a first device region of a semiconductor on insulator (SOI) substrate, wherein the first semiconductor device includes a first source region and a first drain region that is formed in the SOI layer, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer; and forming a second semiconductor device in the second device region of the SOI substrate, wherein the second device includes a second source region and a second drain region that is present in a base semiconductor substrate of the SOI substrate, and a second gate structure including a gate dielectric provided by a buried dielectric layer of the SOI substrate and a gate conductor comprised of a same material as the raised source and drain regions. |
地址 |
Armonk NY US |