Semiconductor Device Having Memory Cell With Electrostatic Capacitance Circuit

摘要

A capacitance coupled to a memory node and a word line of an SRAM cell provides an electrostatic capacitance between the memory node and the word line. The capacitance has a first electrostatic capacitance when the word line is in a nonselective state (usually a LOW level) and the memory node retains a HIGH level; the capacitance has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state (usually the LOW level) and the memory node retains the LOW level.

主权项

1. A semiconductor device comprising:
a word line; a pair of data lines; and a memory cell coupled to the word line and the pair of data lines, the memory cell including:
first and second memory nodes;a flip-flop circuit to set one of the first and second memory nodes at a first potential and the other of the first and second memory nodes at a second potential which is lower than the first potential in response to stored data;a first transfer transistor to control the connection between the first memory node and the first bit line in response to whether the word line is in a selective state or in a nonselective state;a second transfer transistor to control the connection between the second memory node and the second bit line in response to whether the word line is in the selective state or in the nonselective state;a first capacitive element coupled between the first memory node and the word line;a second capacitive element coupled between the second memory node and the word line;a third wiring functioning as a gate electrode for both the first transfer transistor and the first capacitive element; anda fourth wiring functioning as a gate electrode for both the second transfer transistor and the second capacitive element.