Integrated multiple gate length semiconductor device including self-aligned contacts

摘要

A multi-channel semiconductor device includes a first and second gate channels formed in a semiconductor substrate. The first gate channel has a first length and the second gate channel has a second length greater than the first length. A gate dielectric layer is formed in the first and second gate channels. A first plurality of work function metal layers is formed on the gate dielectric layer of the first gate channel. A second plurality of work function metal layers is formed on the gate dielectric layer of the second gate channel. A barrier layer is formed on each of the first and second plurality of work function metal layers, and the gate dielectric layer. The multi-channel semiconductor device further includes metal gate stacks formed on of the barrier layer such that the barrier layer is interposed between the metal gate stacks and the gate dielectric layer.

主权项

1. A method of fabricating a multi-gate semiconductor device, the method comprising:
forming a first gate void in a semiconductor substrate and a second gate void in the semiconductor substrate, the first gate void having a first length and the second gate void a second length greater than the first length; forming a gate dielectric layer in the first and second gate voids; forming a first plurality of work function metal layers on the gate dielectric layer of the first gate void and forming a second plurality of work function metal layers on the gate dielectric layer of the second gate void, the second plurality of work function metal layers including a portion of the first plurality of work function metal layers such that the second plurality of work function metal layers has a greater number of layers than the first plurality of work function metal layers; etching the first plurality of work function metal layers to form a first gate cavity and etching the second plurality of work function metal layers to form a second gate cavity; forming a barrier layer in the first and second gate cavities; and forming metal gate stacks in the first and second cavities and on an exposed surface of the barrier layer, wherein the forming the second plurality of work function metal layers on the gate dielectric layer of the second gate void comprises: forming a first work function metal layer directly on the gate dielectric layer; forming a second work function metal layer on the first work function metal layer; forming a third work function metal layer on the second work function metal layer; and forming a fourth work function metal layer on the third work function metal layer.