发明名称 Memory device comprising a transistor including an oxide semiconductor and semiconductor device including the same
摘要 A memory device consumes low power, has high capacity, and is shared by a plurality of processors. A data write transistor of a memory device is manufactured with a material capable of achieving a sufficiently low off-state current of a transistor (e.g., an oxide semiconductor material that is a wide band gap semiconductor). The memory device has a memory cell including at least one data write transistor, at least one data storage transistor, and at least two data read transistors.
申请公布号 US9287370(B2) 申请公布日期 2016.03.15
申请号 US201313772530 申请日期 2013.02.21
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Kurokawa Yoshiyuki
分类号 G11C11/00;H01L29/26;H01L29/24;H01L27/12;G11C8/16;H01L27/11;H01L27/115 主分类号 G11C11/00
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A memory device comprising: a first transistor including a first channel formation region; a second transistor including a second channel formation region; a third transistor including a third channel formation region; a fourth transistor including a fourth channel formation region; a first line; a second line; a third line; a fourth line; a fifth line; a sixth line; and a seventh line, wherein one of a source and a drain of the first transistor is electrically connected to the first line, wherein one of a source and a drain of the second transistor is electrically connected to the second line, wherein one of a source and a drain of the third transistor is electrically connected to the third line, wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth line, wherein a gate of the first transistor is electrically connected to the fifth line, wherein a gate of the third transistor is electrically connected to the sixth line, wherein a gate of the fourth transistor is electrically connected to the seventh line, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor so that a node is formed, wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor, wherein the first channel formation region includes a semiconductor material that is different from a semiconductor material in the second channel formation region, the third channel formation region and the fourth channel formation region, and wherein the first channel formation region includes an oxide semiconductor.
地址 Atsugi-shi,Kanagawa-ken JP