Current-Mode Sense Amplifier

摘要

A current sense amplifier comprises a reference current input terminal, a control line input terminal, a sense current input terminal, an output terminal, a first NAND gate, a transmission gate, and two cross coupled inverters each comprising a n-FET. The first NAND gate comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate comprises two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal. Sources of the n-FETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively.

主权项

1. A current sense amplifier, comprising:
a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal, the amplifier further comprising:a first NAND gate comprising a second output terminal being coupled to the first output terminal of the amplifier;a first cross coupled inverter comprising a first n-FET and a second cross coupled inverter comprising a second n-FET;a transmission gate comprising first and second transmission terminals and a gate terminal, the gate terminal coupled to the control line terminal;
wherein a first source of the first n-FET is coupled to the sense current input terminal and a second source of the second n-FET is coupled to the reference current input terminal, wherein, the first transmission terminal is coupled to a first input terminal of the first cross coupled inverter and the second transmission terminal is coupled to a second input terminal of the second cross coupled inverter; and wherein at least a first input terminal of the first NAND gate is coupled to the control line terminal and at least a second input terminal of the first NAND gate is coupled to at least one of the input terminals of the inverters.