DELAY CIRCUITS AND RELATED SYSTEMS AND METHODS

摘要

Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

主权项

1. A delay circuit for delaying an output enable signal, comprising:
a first shift register chain comprising:
a first chain input configured to receive an output enable in signal, wherein the output enable in signal is based on a slow clock signal;a first chain clock input configured to receive a fast clock signal; anda first chain output configured to provide a first strobe signal; a second shift register chain comprising:
a second chain input configured to receive the output enable in signal;a second chain clock input configured to receive the fast clock signal; anda second chain output configured to provide a second strobe signal, wherein each transition of the second strobe signal is opposite of a corresponding transition of the first strobe signal; and a delayed output configured to provide an output enable out signal based on the first strobe signal, the second strobe signal, and the output enable in signal.