| 摘要 |
Embodiments are disclosed that relate to multi-phase clock generators (174, 184) and data samplers (142, 156) for use in high speed I/O circuitry (100). One disclosed example provides a multi-phase clock generator (174) including a delay line (fig: 2 202a, b) having a plurality of delay elements, the delay line being configured to receive an input clock signal and output a plurality of output clock signals (fig. 2: CLK0-9) having different phases compared to a phase of the input clock signal. The multi-phase clock generator (fig. 2: 200) further includes a control circuit (fig. 2: 204) configured to control the delay line based at least in part upon rising edges and falling edges of one or more output clock signals (fig. 2: CLK0, 5 and TCLK0, 5) output at one or more locations along the delay line. |
