| 摘要 |
A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. The low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. In some applications where only the integrated circuit can read the data, a second control signal internal to the integrated circuit generates start, stop, device ID, read pattern, starting address, and actual read cycles, while the first control signal external to the integrated circuit can do the same for the program or erase path. Since the clock signal can be derived and shared from the system clock of the integrated circuit, the NVM memory need only have one external control pin for I/O transactions to realize a low-pin-count interface. |
| 主权项 |
1. A low-pin-count non-volatile memory (NVM) integrated in an integrated circuit comprises:
a plurality of NVM cells; a clock signal internal to the integrated circuit coupled to a system clock of the integrated circuit; and a control signal external to the integrated circuit to generate start, stop, read, program, or erase conditions with timing related to the clock signal for read, program, or erase condition; wherein the program or erase period being determined by the pulse width of the clock signal and whether an NVM cell being programmed or not determined by the control signal when the clock toggles after the program or erase begins. |
