Semiconductor device having data terminal supplied with plural write data in serial

摘要

Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit. The data output circuit outputs read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal. The data input circuit outputs write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals.

主权项

1. A semiconductor device comprising:
first and second opposing sides elongated in a first direction, the first and second sides being parallel to each other; a first peripheral circuit region located closer to the first side than the second side, wherein the first peripheral circuit region comprises clock input circuitry configured to receive an external clock signal and generate a first clock signal and a frequency dividing circuit configured to generate one or more frequency-divided second clock signals by dividing a frequency of the first clock signal; a second peripheral circuit region located closer to the second side than the first side, wherein the second peripheral circuit region comprises a multiplier circuit configured to receive the one or more second clock signals and generate a third clock signal; and at least one clock line extending from the first peripheral circuit region to the second peripheral circuit region, wherein at least one of the second clock signals is transmitted from the frequency dividing circuit to the multiplier circuit by the at least one clock line.