发明名称 Method and circuit for scalable cross point switching using 3-D die stacking
摘要 A cross-point switch having stacked switching dies on a component die is disclosed. The cross point switch allows scalability by adding switching dies. The switching dies include ingress switches that are coupled to multiplexers to a middle stage switches. The inputs and outputs of the ingress switches are connected to the switching interface region via through silicon vias (TSVs). The outputs of the ingress switches are also coupled by TSVs to multiplexers for routing to middle stage switches on a switching die above. If the switching die is stacked on another switching die, the outputs of the ingress switches are coupled by TSVs to the multiplexers for routing to the middle stage switches of the switching die below. By adding switching dies, the switch is configurable to increase the number of ports as well as the width of the ports.
申请公布号 US9276582(B2) 申请公布日期 2016.03.01
申请号 US201514791917 申请日期 2015.07.06
申请人 Altera Corporation 发明人 Schulz Jeffrey;Hutton Michael
分类号 G06F13/40;H03K19/173;H03K19/177;G06F15/173 主分类号 G06F13/40
代理机构 Nixon Peabody LLP 代理人 Nixon Peabody LLP
主权项 1. A configurable system allowing cross switching between components, the system comprising: a switching interface region on a substrate, the switching interface region including a plurality of input ports coupled to a first plurality of electronic components and a plurality of output ports coupled to a second plurality of electronic components; a first switching die above the substrate, the first switching die including a plurality of ingress stage switches each having inputs and outputs and a plurality of middle stage switches each having inputs and outputs, each of the outputs of the middle stage switches coupled to one of the plurality of output ports; a plurality of multiplexers each having a first input coupled to an output of a respective one of the plurality of ingress stage switches and an output coupled to an input of a respective one of the plurality of the middle stage switches; a first plurality of input through-silicon vias (TSV) each coupled between a respective one of a first subset of the plurality of input ports in the switching interface region and an input of a respective one of the plurality of ingress stage switches; and a second plurality of input TSVs each coupled between a respective one of a second subset of the plurality of input ports in the switching interface region and a second input of each of the plurality of multiplexers, wherein the plurality of multiplexers control the inputs to the plurality of middle stage switches to route signals between the first plurality of electronic components and the second plurality of electronic components.
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