| 发明名称 | Time division multiplexed limited switch dynamic logic | ||
| 摘要 | A dynamic logic circuit includes a precharge device configured to precharge a dynamic node in accordance with a first and second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first value in response to one or more first input signals in accordance with the first evaluation clock signal. A second evaluation tree configured to evaluate the dynamic node to a second value in response to one or more second input signals in accordance with the second evaluation clock signal. | ||
| 申请公布号 | US9276580(B2) | 申请公布日期 | 2016.03.01 |
| 申请号 | US201514660474 | 申请日期 | 2015.03.17 |
| 申请人 | INTERNATIONAL BUSINESS MACHINES CORPORATION | 发明人 | Chang Leland;Montoye Robert K.;Nakamura Yutaka |
| 分类号 | H03K19/096 | 主分类号 | H03K19/096 |
| 代理机构 | Tutunjian & Bitetto, P.C. | 代理人 | Tutunjian & Bitetto, P.C. ;Alexanian Vazken |
| 主权项 | 1. A dynamic logic circuit including: a precharge device configured to precharge a dynamic node in accordance with a first and second evaluation clock signal; a first evaluation tree configured to evaluate the dynamic node to a first value in response to one or more first input signals in accordance with the first evaluation clock signal; and a second evaluation tree configured to evaluate the dynamic node to a second value in response to one or more second input signals in accordance with the second evaluation clock signal. | ||
| 地址 | Armonk NY US | ||