| 发明名称 | Selective test pattern processor | ||
| 摘要 | A method, system, and computer program product to test a semiconductor device are described. The system includes an input interface to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns. The system also includes a processor to process the subset of the set of test patterns to output test data to the semiconductor device. | ||
| 申请公布号 | US9274173(B2) | 申请公布日期 | 2016.03.01 |
| 申请号 | US201414502182 | 申请日期 | 2014.09.30 |
| 申请人 | International Business Machines Corporation | 发明人 | Forlenza Donato O.;Forlenza Orazio P.;Grace Michael P.;Robbins Bryan J. |
| 分类号 | G01R31/3177;G01R31/28;G06F11/25;G01R31/3183 | 主分类号 | G01R31/3177 |
| 代理机构 | Cantor Colburn LLP | 代理人 | Cantor Colburn LLP ;McNamara Margaret |
| 主权项 | 1. A system to test a semiconductor device, comprising: an input interface configured to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns; and a processor configured to process the subset of the set of test patterns to output test data to the semiconductor device, wherein the processor processing the subset of the set of test patterns includes cataloging a content of pattern files corresponding with the subset of the set of test patterns by listing the content of pattern files corresponding with the subset of the set of test patterns to generate a catalog. | ||
| 地址 | Armonk NY US | ||