发明名称 |
Apparatus, method, and system for instantaneous cache state recovery from speculative abort/commit |
摘要 |
An apparatus and method is described herein for providing instantaneous, efficient cache state recover upon an end of speculative execution. Speculatively accessed entries of a cache memory are marked as speculative, which may be on a thread specific basis. Upon an end of speculation, the speculatively marked entries are transitioned in parallel by a speculative port to their appropriate, thread specific, non-speculative coherency state; these parallel transitions allow for instantaneous commit or recovery of speculative memory state. |
申请公布号 |
US9274962(B2) |
申请公布日期 |
2016.03.01 |
申请号 |
US201012961767 |
申请日期 |
2010.12.07 |
申请人 |
Intel Corporation |
发明人 |
Nimmala Prashanth;Bonakdar Hamid-Reza S. |
分类号 |
G06F12/00;G06F12/08;G06F9/30 |
主分类号 |
G06F12/00 |
代理机构 |
Lowenstein Sandler, LLP |
代理人 |
Lowenstein Sandler, LLP |
主权项 |
1. An apparatus comprising: a cache memory including data storage including a first data entry and a second data entry;
state storage associated with the data storage, the state storage including a first state entry to hold a first processing element speculative value to indicate a first processing element has speculatively accessed the first data entry and a second state entry to hold the first processing element speculative value to indicate the first processing element speculatively accessed the second data entry, wherein the state storage further comprises a coherency storage structure to hold a coherency state for the first state entry and for the second state entry, and a speculative storage structure to hold speculative values of the first state entry and for the second state entry; and a first speculative port operatively coupled to the first state entry and a second speculative port operatively coupled to the second state entry, the first and second speculative ports including speculative algorithm logic to:
transition the first and second state entries from the first processing element speculative value to a first processing element non-speculative value in one cycle in response to an end of speculative execution event associated with the first processing element;modify the coherency storage structure to hold a coherency value based on the first processing element speculative value and the end of speculation execution event; andwrite the first processing element non-speculative value to the speculative storage structure, wherein the combination of the coherency value held in the coherency storage structure and the first processing element non-speculative value held in the speculative storage structure forms the first processing element non-speculative value. |
地址 |
Santa Clara CA US |