发明名称 MEMORY CIRCUITS AND METHOD FOR ACCESSING DATA OF THE MEMORY CIRCUITS
摘要 A memory circuit includes a memory cell, a first bit line, a first bit line bar, a sense amplifier, a first switch and a second switch. The memory cell is coupled with a first bit line having a first bit line portion and a second bit line portion. The first bit line bar has a first bit line bar portion and a second bit line bar portion. The sense amplifier includes a read/write circuit configured to couple the second bit line portion to a global bit line. The first switch is coupled between the first bit line bar portion and the second bit line bar portion. The second switch is coupled between the first bit line portion and the second bit line portion.
申请公布号 US2016055887(A1) 申请公布日期 2016.02.25
申请号 US201514929511 申请日期 2015.11.02
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 KATOCH Atul
分类号 G11C7/06 主分类号 G11C7/06
代理机构 代理人
主权项 1. A memory circuit comprising: a memory cell coupled with a first bit line having a first bit line portion and a second bit line portion; a first bit line bar having a first bit line bar portion and a second bit line bar portion; a sense amplifier comprising a read/write circuit being configured to couple the second bit line portion to a global bit line; a first switch coupled between the first bit line bar portion and the second bit line bar portion, the first switch being configured to electrically isolate the sense amplifier from the first bit line bar portion after a first time interval, where a first voltage difference between the second bit line portion and the second bit line bar portion is substantially equal to or larger than a predetermined value; and a second switch coupled between the first bit line portion and the second bit line portion, the second switch being configured to (1) electrically isolate the sense amplifier from the first bit line portion based on a received signal during the first time interval, and to (2) electrically couple the first bit line portion and the sense amplifier during a second time interval, where the read/write circuit is operated to couple the second bit line portion and the global bit line.
地址 Hsinchu TW