发明名称 Methods of fabricating semiconductor devices
摘要 A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.
申请公布号 US9269720(B1) 申请公布日期 2016.02.23
申请号 US201514729111 申请日期 2015.06.03
申请人 Samsung Electronics Co., Ltd. 发明人 Bae Jin-woo;Kwon Byoung-ho;Park Jong-hyuk;Park Hye-sung;Lee Jun-seok;Im Ki-vin;Cheon Hee-sook;Hwang In-seak
分类号 H01L27/10;H01L27/115;H01L29/66;H01L21/768;H01L21/3105;H01L21/311;H01L21/31;H01L21/3213;H01L21/3205 主分类号 H01L27/10
代理机构 Myers Bigel Sibley, P.A. 代理人 Myers Bigel Sibley, P.A.
主权项 1. A method of fabricating a semiconductor device, comprising: providing a substrate having a cell region and a peripheral circuit region; forming a plurality of bit line structures on the substrate in the cell region and a gate structure having the same structure as each of the bit line structures on the substrate in the peripheral circuit region, the plurality of bit line structures extending in a first direction and being spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction; forming spacers on sidewalls of the bit line structures and sidewalls of the gate structure; forming a sacrificial layer in the first grooves, wherein the sacrificial layer covers top surfaces of the bit line structures and the gate structure; and planarizing the sacrificial layer until the top surfaces of the bit line structures and the gate structure are exposed.
地址 KR