发明名称 Techniques for managing system power using deferred graphics rendering
摘要 An apparatus may include a memory to store one or more graphics rendering commands in a queue after generation. The apparatus may also include a processor circuit, and a graphics rendering command manager for execution on the processor to dynamically determine at one or more instances a total execution duration for the one or more graphics rendering commands, where the total execution duration comprises a total time to render the one or more graphics rendering commands. The graphics rendering command manager also may be for execution on the processor to generate a signal to transmit the one or more graphics rendering commands for rendering by a graphics processor when the total execution duration exceeds a graphics rendering command execution window.
申请公布号 US9269121(B2) 申请公布日期 2016.02.23
申请号 US201213718794 申请日期 2012.12.18
申请人 INTEL CORPORATION 发明人 Jeganathan Nithyananda S.;Poornachandran Rajesh;Diefenbaugh Paul S.;Han Kyungtae
分类号 G06T1/20;G06F1/32 主分类号 G06T1/20
代理机构 Kacvinsky Daisak Bluni PLLC 代理人 Kacvinsky Daisak Bluni PLLC
主权项 1. An apparatus, comprising: a memory to store one or more graphics rendering commands in a queue after generation; a processor; and a graphics rendering command manager for execution on the processor to: dynamically determine at one or more instances in a graphics frame a total execution duration for the one or more graphics rendering commands, the total execution duration comprising a total time to render the one or more graphics rendering commands; andgenerate a signal to transmit the one or more graphics rendering commands for rendering by a graphics processor and to wake up the graphics processor from a low power state when the total execution duration exceeds a graphics rendering command execution window based on a decreasing remaining interval before an end of the graphics frame and based on an amount of time required to wake up the graphics processor from the low power state.
地址 Santa Clara CA US