Detecting defective connections in stacked memory devices

摘要

A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.

主权项

1. A method for testing a stacked memory device having a plurality of memory chips arranged on top of, and having connections to, a logic chip, for a connection defect, comprising:
performing a first test of a first memory chip of the plurality of memory chips by:
writing a first write data value, designed to reveal a connection defect, into a first location in the first memory chip;reading a first read data value from the first location in the first memory chip;detecting a first bit error corresponding to the first location in the first memory chip; andrecording, in response to the first bit error, a first bit number corresponding to the first bit error; performing a second test of the first memory chip by:
writing a second write data value into a second location in the first memory chip;reading a second read data value from the second location in the first memory chip;detecting a second bit error corresponding to the second location in the first memory chip; and,recording, in response to the second bit error, a second bit number corresponding to the second bit error; and, replacing, in response to a first recorded bit number being equal to a second recorded bit number, a connection common to the first and second bit errors, with a spare connection.