Controlling Reduced Power States Using Platform Latency Tolerance

摘要

In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a plurality of cores; power management logic to:
determine whether bus traffic is below a defined threshold level during a reduced power state in the processor;in response to a determination that the bus traffic is below the defined threshold level during the reduced power state in the processor, block a first plurality of break events from interrupting the reduced power state in the processor;in response to a first break event during the reduced power state in the processor, set an exit timer based on a platform latency tolerance and a wake time; andin response to an expiration of the exit timer, terminate the reduced power state in the processor.