| 摘要 |
A memory device (and method of operation) such as a cache memory L1 (16 figure 1) comprising a plurality of storage units 44 and access control circuitry 42. The access control 22 is configured to receive an access request and in response to the access request to initiate an access procedure in each of the storage units. The access control circuitry 22 is configured to receive an access (late) kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units (timing in figure 4). Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time (performance speed) for the memory device is kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced. The storage unit may, via wordline circuitry, activate a selected wordline, based on an access request, but further suppress selected wordlines in response to the access kill signal. The suppression circuit may be a MOSFET transistor 68 connecting the selected wordline to a fixed voltage, ground or Vss, disabling bitcell 46 cell access. Alternatively or in addition, the sense amplifier may be initiated by a sense amplifier enable signal, but selected amplifiers may be disabled by the kill signal, (e.g MOSFET switch shorting sense amplifier enable signal to Vss). The memory device may be a first level cache associated with a data processor. This may also be a multi-way set associative cache system employing way prediction circuitry, and may comprise a tag storage unit as well as a data storage unit, utilised to reach a decision on the issuing of a kill signal. Access suppression occurs after the first edge of an internally generated clock signal raised to initiate the access procedure in the plurality of storage units. |
