| 发明名称 |
DATA PREFETCH RAMP IMPLEMENATION BASED ON MEMORY UTILIZATION |
| 摘要 |
A technique for data prefetching for a multi-core chip includes determining memory utilization of the multi-core chip. In response to the memory utilization of the multi-core chip exceeding a first level, data prefetching for the multi-core chip is modified from a first data prefetching arrangement to a second data prefetching arrangement to minimize unused prefetched cache lines. In response to the memory utilization of the multi-core chip not exceeding the first level, the first data prefetching arrangement is maintained. The first and second data prefetching arrangements are different. |
| 申请公布号 |
US2016034400(A1) |
申请公布日期 |
2016.02.04 |
| 申请号 |
US201414445214 |
申请日期 |
2014.07.29 |
| 申请人 |
International Business Machines Corporation |
发明人 |
DALE JASON NATHANIEL;DOOLEY MILES R.;EICKEMEYER, JR. RICHARD J.;GRISWELL, JR. JOHN BARRY;O'CONNELL FRANCIS PATRICK;STUECHELI JEFFREY A. |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of data prefetching for a multi-core chip, comprising:
determining memory utilization of the multi-core chip; in response to the memory utilization of the multi-core chip exceeding a first level, modifying data prefetching for the multi-core chip from a first data prefetching arrangement to a second data prefetching arrangement to minimize unused prefetched cache lines; and in response to the memory utilization of the multi-core chip not exceeding the first level, maintaining the first data prefetching arrangement, wherein the first and second data prefetching arrangements are different. |
| 地址 |
Armonk NY US |
