发明名称 CACHE-COHERENT MULTIPROCESSOR SYSTEM AND A METHOD FOR DETECTING FAILURES IN A CACHE-COHERENT MULTIPROCESSOR SYSTEM
摘要 A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.
申请公布号 US2016034398(A1) 申请公布日期 2016.02.04
申请号 US201414445237 申请日期 2014.07.29
申请人 WENDEL DIRK;BIBEL OLIVER;FADER JOACHIM;VON WENDORFF WILHARD CHRISTOPHORUS 发明人 WENDEL DIRK;BIBEL OLIVER;FADER JOACHIM;VON WENDORFF WILHARD CHRISTOPHORUS
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项 1. A cache-coherent multiprocessor system comprising a first processing unit and a second processing unit, a shared memory resource accessible by the first processing unit and the second processing unit, the shared memory resource being divided into at least one shared region, at least one first region assigned to the first processing unit, and at least one second region assigned to the second processing unit,a first cache related to the first processing unit,a second cache related to the second processing unit,a coherency unit, anda monitor unit, wherein the coherency unit is adapted to secure the cache-coherency of the cache-coherent multiprocessor system, and wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit.
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