发明名称 |
ADDRESS TRANSLATION CACHE THAT SUPPORTS SIMULTANEOUS INVALIDATION OF COMMON CONTEXT ENTRIES |
摘要 |
A processor includes a mapping module that maps architectural virtual processor identifiers to non-architectural global identifiers and maps architectural process context identifiers to non-architectural local identifiers. The processor also includes a translation-lookaside buffer (TLB) having a plurality of address translations. For each address translation of the plurality of address translations: when the address translation is a global address translation, the address translation is tagged with a representation of one of the non-architectural global identifiers to which the mapping module has mapped one of the virtual processor identifiers; and when the address translation is a local address translation, the address translation is tagged with a representation of one of the non-architectural local identifiers to which the mapping module has mapped one of the process context identifiers. |
申请公布号 |
WO2016012832(A1) |
申请公布日期 |
2016.01.28 |
申请号 |
WO2014IB03116 |
申请日期 |
2014.11.26 |
申请人 |
VIA ALLIANCE SEMICONDUCTOR CO., LTD. |
发明人 |
EDDY, COLIN;MOHAN, VISWANATH |
分类号 |
G06F12/10 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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