发明名称 |
LOW POWER AND COMPACT AREA DIGITAL INTEGRATOR FOR A DIGITAL PHASE DETECTOR |
摘要 |
In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal. |
申请公布号 |
EP2853030(A4) |
申请公布日期 |
2016.01.27 |
申请号 |
EP20130794113 |
申请日期 |
2013.05.17 |
申请人 |
FINISAR CORPORATION |
发明人 |
NGUYEN, THE'LINH;TROYER, STEVEN, GREGORY;CASE, DANIEL, K. |
分类号 |
H03L7/085;H03L7/093 |
主分类号 |
H03L7/085 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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