发明名称 |
Time-to-voltage converter using a capacitor based digital to analog converter for quantization noise cancellation |
摘要 |
Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-based digital to analog converter (DAC). A phase error is detected between a reference signal and a feedback signal in the PLL. A charge pump circuit charges a first capacitor circuit based on the phase error to generate a phase error voltage corresponding to the phase error. The capacitor based DAC generates a quantization error correction voltage based on a digital value corresponding to the quantization error, which is then combined with the phase error voltage to cancel the quantization error. |
申请公布号 |
US9246500(B2) |
申请公布日期 |
2016.01.26 |
申请号 |
US201414448466 |
申请日期 |
2014.07.31 |
申请人 |
Silicon Laboratories Inc. |
发明人 |
Perrott Michael H. |
分类号 |
H03L7/06;H03L7/093;H03L7/08;H03M1/08;H03M1/66;G04F10/00;H03L7/099;H03M3/00;H03L7/085;H02M3/07 |
主分类号 |
H03L7/06 |
代理机构 |
Abel Law Group, LLP |
代理人 |
Abel Law Group, LLP |
主权项 |
1. A phase-locked loop (PLL) comprising:
a capacitor based digital to analog converter (DAC) coupled to receive a digital indication of quantization noise and to supply a quantization noise correction voltage to adjust a phase error voltage to create a combined voltage with reduced quantization noise, wherein the phase error voltage is indicative of a phase error corresponding to a time difference between a reference signal and a feedback signal from an oscillator controlled at least in part based on a value of the combined voltage. |
地址 |
Austin TX US |