Method for driving arithmetic processing unit

摘要

In a memory cell including an inverter, a capacitor is provided. When the memory cell is not accessed, data stored in the memory cell is copied to the capacitor and then power supply to the inverter is stopped. When the memory cell needs to be accessed, the data is returned from the capacitor to the inverter. In this manner, power consumption when the memory cell is not accessed is reduced. Furthermore, in a memory device including a plurality of such memory cells, backup of the first memory cell and backup of the second memory cell are performed at different timings. Recovery of the first memory cell and recovery of the second memory cell are also performed at different timings. Consequently, power required for backup or recovery can be distributed. Other embodiments may be described and claimed.

主权项

1. A method for driving an arithmetic processing unit, the arithmetic processing unit including a first memory cell and a second memory cell, the first memory cell and the second memory cell each including: a transistor; a capacitor; a first inverter an output of which is input to the capacitor through the transistor; and a second inverter an output of which is directly or indirectly input to the first inverter and an input of which is directly or indirectly output from the first inverter, the method comprising the steps of:
turning on the transistor of the first memory cell at a first time; stopping power supply to at least one of the first inverter and the second inverter of the first memory cell at a second time; turning on the transistor of the second memory cell at a third time; and stopping power supply to at least one of the first inverter and the second inverter of the second memory cell at a fourth time, wherein the first time is earlier than the third time, and wherein the second time is earlier than the fourth time.