SYSTEMS AND METHODS FOR CHIP TO CHIP COMMUNICATION

摘要

Systems and methods for chip to chip communication are disclosed. In an exemplary aspect, a chip to chip link comprises a master device having a data transmitter, a clock, a clock transmitter, a phase locked loop (PLL) associated with the clock, and a receiver. The chip to chip link also comprises a slave device that has a data transmitter, a clock receiver, and a data receiver. Noticeably absent from the slave device is a clock or a PLL. By removing the clock from the slave device, the slave device does not have the power consuming element of a slave PLL. Further, because the slave device does not have a clock which would normally have to acquire a new frequency and settle, the master clock may change frequency relatively quickly and vary the frequency across many frequencies, not just one or two predefined frequencies.

主权项

1. A master integrated circuit (IC) comprising:
a bus interface configured to be coupled to an interchip bus; a transmitter comprising a driver, the driver outputting a data signal to the bus interface for transmission across the interchip bus; a receiver coupled to the bus interface; a clock data recovery (CDR) circuit operatively coupled to the receiver; a phase locked loop (PLL) receiving a reference clock signal and outputting a clock signal to the driver of the transmitter and the CDR circuit, wherein the transmitter outputs a master clock signal onto the interchip bus through the bus interface; and a control system operatively coupled to the PLL and the CDR circuit, the control system configured to change a frequency of the master clock signal by controlling the PLL, wherein data transmission continues during frequency change independent of clock activity at a remote slave IC.