INTEGRATED CLOCK DIFFERENTIAL BUFFERING

摘要

A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal and generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal and to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and provide a first differential reference clock signal corresponding. A second set of clock signal output buffers is coupled to receive the second reference clock signal and provide a second differential reference clock signal. The first and second PLL circuits, and the first and second sets of output buffers reside within an integrated circuit package having a die to receive at least the first differential reference clock signal.