发明名称 |
Nonvolatile semiconductor memory device and method of manufacturing the same |
摘要 |
According to an embodiment, a nonvolatile semiconductor memory device comprises a memory area, a capacitor area, and a transistor area, on a semiconductor substrate. The nonvolatile semiconductor memory device comprises a memory cell and a select gate transistor, in the memory area. The nonvolatile semiconductor memory device includes a capacitor comprising a first electrode layer and a second electrode layer stacked on the first electrode layer via an insulating layer. An upper surface of the capacitor is covered by a first insulating layer, and the insulating layer has an upper level portion and a lower level portion. A part of an outline of the upper level portion is along a part of an outline of the second electrode layer. |
申请公布号 |
US9240417(B1) |
申请公布日期 |
2016.01.19 |
申请号 |
US201514630079 |
申请日期 |
2015.02.24 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
Kikuchi Kenrou;Matsuno Koichi |
分类号 |
H01L27/115;H01L27/108 |
主分类号 |
H01L27/115 |
代理机构 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A method of manufacturing a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device comprising: a memory area including a plurality of memory cells each comprising a charge accumulation layer, and a select gate transistor; a capacitor area including a capacitor; and a transistor area including a control transistor, on a semiconductor substrate, the method comprising:
depositing a first insulating layer, a first conductive layer, and a second insulating layer on the semiconductor substrate; removing at least part of the second insulating layer in a portion of the memory area where the select gate transistor is formed and in the transistor area; depositing a second conductive layer on the semiconductor substrate; dividing the first conductive layer and the second conductive layer to form the plurality of memory cells; removing the second conductive layer at a certain position of the memory area, the capacitor area and the transistor area, and forming a first trench that divides the second conductive layer in the capacitor area, to form the capacitor; selectively removing the second insulating layer and the first conductive layer at least at a position where the adjacently formed select gate transistors are divided, to form the select gate transistor. |
地址 |
Minato-ku JP |