发明名称 SQUARE ROOT ARITHMETIC SYSTEM
摘要 PURPOSE:To perform the square root arithmetic at high speed by obtaining the temporary square root of data from a data table and then obtaining a real square root through the convergent calculation using a recurrence formula. CONSTITUTION:The n-bit data X<2> is supplied and the square root of upper 16 bits of the data X<2> is retrieved out of a data table. Then the lower (n-16)bits of the data X<2> are all set at 0. Thus the square root X1 of the data X<2>1 is obtained. Here the retrieved square root is shifted by (n-16)/2 bits and (n-15)/2 bits when the remaining (n-16) bits are even or odd respectively. Thus a square root X1 is obtained. In the same way, the square root X2 of the data X<2>2 is obtained when lower (n-32) bits of the data (X<2>-X<2>1) are all set at 0. Then the initial value Xe(0) of the repetitive arithmetic is set equal to (X1+X2) with a desired square root set at Xe(n). An equation I is calculated and the convergence of an equation 2 is decided. if the convergence of the equation 2 is confirmed, the Xe(n) of that time point is defined as the square root X of the data X<2>.
申请公布号 JPS62182841(A) 申请公布日期 1987.08.11
申请号 JP19850215193 申请日期 1985.09.30
申请人 YASKAWA ELECTRIC MFG CO LTD 发明人 YAMANAKA MAMORU
分类号 G06F7/552 主分类号 G06F7/552
代理机构 代理人
主权项
地址