Semiconductor device including stacked semiconductor chips without occurring of crack

摘要

A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns. Remaining one or ones of the wiring patterns is kept covered by the insulating layer and includes the first wiring pattern.

主权项

1. A device comprising:
a first semiconductor chip including an edge defining a periphery of the first semiconductor chip; and a second semiconductor chip that is greater in size than the first semiconductor chip, the second semiconductor chip having TSVs (Through Silicon Vias) and being stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip; the second semiconductor chip comprising:
a main surface;a first plurality of upper layer wiring patterns positioning over the edge of the first semiconductor chip in top view;a second plurality of upper layer wiring patterns positioning off the edge of the first semiconductor chip in top view;a first insulating film formed on the main surface, the first insulating film covering over the first plurality of upper layer wiring patterns and the second plurality of upper layer wiring patterns, the first insulating film including one or more holes exposing a portion of a surface of the second plurality of upper layer wiring patterns, the one or more holes for being penetrated by a plurality of surface bump electrodes contacting with the second plurality of upper layer wiring patterns respectively.