Systems and Methods of Sectioned Bit Line Memory Arrays, Including Hierarchical and/or Other Features

摘要

A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.

主权项

1. An SRAM memory device comprising:
a local section bit line including:
a plurality of sectioned bit lines (SBLs), each comprising:
a local bit line;one or more memory cells connected to the local bit line;a local complement bit line connected to the memory cell; &a pass gate coupled to the local bit line;a local sense amplifier;a local shared data driver;a global bit line; wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line.