发明名称 Low voltage diode with reduced parasitic resistance and method for fabricating
摘要 <p>A method of making a diode begins by depositing an Al x Ga 1-x N nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer (112), an n- GaN layer (110), an Al x Ga 1-x N barrier layer (108), and an SiO 2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal (106) deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au-Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n-, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal (106); and an ohmic (114) contact is deposited on the n+ layer (112).</p>
申请公布号 EP1947700(B1) 申请公布日期 2016.01.06
申请号 EP20070254498 申请日期 2007.11.16
申请人 CREE, INC. 发明人 PARIKH, PRIMIT;HEIKMAN, STEN
分类号 H01L29/872;H01L21/329 主分类号 H01L29/872
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