| 摘要 |
A microprocessor comprises an instruction execution unit operable to generate an intermediate result vector and a plurality of calculation control indicators and storage external to the instruction execution unit which stores the intermediate result vector and the plurality of calculation control indicators. The intermediate result vector is generated from an application of at least a first arithmetic operation of a compound arithmetic operation. The calculation control indicators indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The subsequent calculations may involve one or more remaining arithmetic operations of the compound arithmetic operation. The intermediate result vector, in combination with the plurality of calculation control indicators, provides sufficient information to generate a result indistinguishable from an infinitely precise calculation of the compound arithmetic operation whose result is reduced in significance to a target data size. |
