Hybrid CMOS nanowire mesh device and FINFET device

摘要

A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.

主权项

1. A semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate comprising:
a first portion of the SOI substrate containing at least one nanowire mesh device and a second portion of the SOI substrate containing at least one FINFET device; the at least one nanowire mesh device comprising: a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region and a trench isolation region; the at least one FINFET device comprising: a plurality of spaced apart fins on a top semiconductor layer on the second portion of the substrate; a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of fins and a trench isolation region; wherein the SOI substrate comprises a semiconductor base, a buried insulating layer and a top semiconductor layer such that a thickness of the top semiconductor layer in the second portion is greater than the top semiconductor layer in the first portion and the top semiconductor layer in the first portion and the second portion makes direct contact with the trench isolation region in the nanowire mesh device and the at least one FINFET device respectively.