发明名称 CACHE LOAD BALANCING IN STORAGE CONTROLLERS
摘要 Methods and structure are provided for cache load balancing in storage controllers that utilize Solid State Drive (SSD) caches. One embodiment is a storage controller of a storage system. The storage controller includes a host interface operable to receive Input and Output (I/O) operations from a host computer. The storage controller also includes a cache memory that includes an SSD. Further, the storage controller includes a cache manager that is distinct from the cache memory. The cache manager is able to determine physical locations in the multiple SSDs that are unused, to identify an unused location that was written to a longer period of time ago than other unused locations, and to store a received I/O operation in the identified physical location. Further, the cache manager is able to trigger transmission of the stored I/O operations to storage devices of the storage system for processing.
申请公布号 US2015378947(A1) 申请公布日期 2015.12.31
申请号 US201514795543 申请日期 2015.07.09
申请人 Avago Technologies Limited 发明人 Maharana Parag R.;Sampathkumar Kishore K.
分类号 G06F13/28;G06F12/08;G06F13/42;G06F12/02 主分类号 G06F13/28
代理机构 代理人
主权项 1. A storage controller of a storage system, the storage controller comprising: a host interface operable to receive Input/Output (I/O) operations from a host computer; a cache memory comprising a Solid State Drive (SSD); and a cache manager that is operable to determine physical locations in the SSD that are unused, to identify an unused location that was written to a longer period of time ago than other unused locations, and to store a received I/O operation in the identified physical location, the cache manager further operable to trigger transmission of stored I/O operations to storage devices of the storage system for processing, wherein if the cache manager identifies cached I/O operations that are directed along signaling pathways that share a common device, the cache manager is operable to interleave other I/O operations between the identified I/O operations, wherein the other I/O operations utilize signaling pathways that do not share the common device.
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