主权项 |
1. A semiconductor integrated circuit device comprising:
a plurality of memory cells arranged along a first direction, each of the plurality of memory cells including first and second storage nodes, a first inverter, an input of which is connected to the first storage node and an output of which is connected to the second storage node, including a first p-channel transistor and a first n-channel transistor, a second inverter, an input of which is connected to the second storage node and an output of which is connected to the first storage node, including a second p-channel transistor and a second n-channel transistor, a third n-channel transistor connected to the first storage node, a fourth n-channel transistor connected to the second storage node, and a gate electrode of the fourth n-channel transistor being connected to a gate electrode of the third transistor; a first bit line connected to the third n-channel transistor of each of the plurality of memory cells; a second bit line connected to the fourth n-channel transistors of the plurality of memory cells; a memory cell power supply line being connected to source electrodes of the first and second p-channel transistors of each of the plurality of memory cells; a power supply line that supplies a power voltage; and a power transistor connected to the memory cell power supply line, the power transistor making an electrical pass between the power supply line and the memory cell power supply line, wherein the plurality of memory cells has a first part, a second part and a third part, wherein the first n-channel transistor and the fourth n-channel transistor are located in the first part, wherein the first p-channel transistor and the second transistor are located in the second part, wherein the second n-channel transistor and the third n-channel transistor are located in the third part. |