Techniques for detection and treating memory hole to local interconnect marginality defects

摘要

Techniques are presented for the determination and handling of defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defects, an AC stress can be applied between the interconnects and the bit lines/NAND strings, after which a defect determination operation can be performed. This technique can also be implemented at the system level by having the controller instruct the memory to perform it as part of an adaptive defect determination operation.

主权项

1. A method of determining defects in a monolithic three-dimensional semiconductor memory device having memory cells arranged in multiple physical levels above a silicon substrate and comprising a charge storage medium, the memory cells being formed into a plurality of NAND strings each connected to an associated one of a plurality of bit lines, wherein the NAND strings are formed above a well structure and run in a vertical direction relative to the substrate and are formed in groups between local interconnect lines that also are formed above the well structure and run in the vertical direction relative to the substrate, and wherein the bit lines run in a horizontal direction relative to the substrate, the method comprising:
performing a first stress operation, including:
placing into a non-conducting state a first set of one or more NAND strings, wherein one or more of the first set of NAND strings are adjacent to one or more of a first set of one or more of the interconnect lines; andconcurrently applying a series of high voltage pulses to the first set of interconnect lines and applying a series of intermediate voltage pulses to a first set one or more bit lines along which are connected the first set of NAND strings, wherein the series of high voltage pulses and series intermediate voltage pulses are out of phase relative to one another; and subsequently performing a first defect determination operation to determine whether a short exists between the first set of bit lines and the first set of interconnect lines.