发明名称 Test apparatus and test module
摘要 A test apparatus that tests a device under test, comprising a control apparatus sequentially executing a plurality of test programs and controlling testing of the device under test; and a test module controlled by the control apparatus to test the device under test by communicating with the device under test and to transmit a test result of each test program to the control apparatus. The test module includes memories that store the test results of the test programs, and starts a subsequent test such that at least a portion of a result processing time period of a current test, from when a test result stored in a first memory begins being transmitted to the control apparatus to when processing of the test result by the control apparatus ends, overlaps with at least a portion of a test execution period in which the subsequent test is executed using a second memory.
申请公布号 US9223670(B2) 申请公布日期 2015.12.29
申请号 US201213427909 申请日期 2012.03.23
申请人 ADVANTEST CORPORATION 发明人 Sugimura Hajime;Yaguchi Takeshi;Nakajima Takahiro
分类号 G06F11/273 主分类号 G06F11/273
代理机构 代理人
主权项 1. A test apparatus that tests a device under test, comprising: a control apparatus that sequentially executes a plurality of test programs and controls testing of the device under test; and a test module that is controlled by the control apparatus to test the device under test by communicating with the device under test and to transmit a test result of each test program to the control apparatus, wherein the test module includes a plurality of memories that store the test results of the test programs, and starts a subsequent test of the device under test such that at least a portion of a result processing time period of a current test of the device under test, which is from when a test result of the current test stored in a first memory begins to be transmitted to the control apparatus to when processing of the test result of the current test by the control apparatus is finished, overlaps with at least a portion of a test execution period of the subsequent test, which is from when the subsequent test is begun to when a test result of the subsequent test is stored in a second memory.
地址 Tokyo JP