发明名称 INSTRUCTION PROCESSING SYSTEM AND METHOD
摘要 An instruction processing system is provided. The system includes a central processing unit (CPU), an m number of memory devices and an instruction control unit. The CPU is capable of being coupled to the m number of memory devices. Further, the CPU is configured to execute one or more instructions of the executable instructions. The m number of memory devices with different access speeds are configured to store the instructions, where m is a natural number greater than 1. The instruction control unit is configured to, based on a track address of a target instruction of a branch instruction stored in a track table, control a memory with a lower speed to provide the instruction for a memory with a higher speed.
申请公布号 US2015370569(A1) 申请公布日期 2015.12.24
申请号 US201414766452 申请日期 2014.01.29
申请人 SHANGHAI XINHAO MICROELECTRONICS CO. LTD. 发明人 LIN KENNETH CHENGHAO
分类号 G06F9/32 主分类号 G06F9/32
代理机构 代理人
主权项 1. An instruction processing system, comprising: m number of memory devices with different access speeds configured to store executable instructions, wherein m is a natural number greater than or equal to two and the m number of memory devices include at least a memory with a lower speed and a memory with a higher speed; a central processing unit (CPU) capable of being coupled to the m number of memory devices, and configured to execute one or more instructions of executable instructions; and an instruction control unit configured to, based on a track address of a target instruction of a branch instruction stored in a track table, control the memory with a lower speed to provide the instructions for the memory with a higher speed.
地址 Shanghai CN