发明名称 |
Method of estimating the signal delay in a VLSI circuit |
摘要 |
A method estimates the signal delay in a VLSI circuit and accurately estimates the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI circuit from erroneously judging the logic made by the designed circuit.
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申请公布号 |
US7600206(B2) |
申请公布日期 |
2009.10.06 |
申请号 |
US20070733030 |
申请日期 |
2007.04.09 |
申请人 |
CHANG GUNG UNIVERSITY |
发明人 |
LAI MING-HONG;HSU CHAO-HSUAN;CHU CHIA-CHI;FENG WU-SHIUNG |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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