发明名称 IMAGE PROCESSING CIRCUIT AND IMAGE ENCODER
摘要 <p><P>PROBLEM TO BE SOLVED: To provide an image processing circuit having a smaller mounting area. <P>SOLUTION: The image processing circuit for obtaining interpolating pixel values from pixel values of pixels arranged in a matrix has: a first arithmetic circuit which obtains a first interpolating pixel value from pixel values in a column by interpolation operation processing; a second arithmetic circuit which obtains a second interpolating pixel value from pixel values in a column adjacent to the column being the processing target of the first arithmetic circuit, by interpolation operation processing; a third arithmetic circuit which obtains a third interpolating pixel value from pixel values in a column adjacent to the column being the processing target of the second arithmetic circuit, by interpolation operation processing; a fourth arithmetic circuit which obtains a fourth interpolating pixel value between columns of pixels processed by the first and second arithmetic circuits from the first interpolating pixel value and the second interpolating pixel value by interpolation operation processing; and a fifth arithmetic circuit which obtains a fifth interpolating pixel value between columns of pixels processed by the second and third arithmetic circuits from the second interpolating pixel value and the third interpolating pixel value by interpolation operation processing. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2011049619(A) 申请公布日期 2011.03.10
申请号 JP20090193850 申请日期 2009.08.25
申请人 FUJITSU LTD 发明人 SO YO
分类号 H04N19/60;H04N11/04;H04N19/42;H04N19/503;H04N19/523;H04N19/59;H04N19/593;H04N19/61;H04N19/625;H04N19/91 主分类号 H04N19/60
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