发明名称 |
Simulation Method Achieving Fast Signal Visibility |
摘要 |
PURPOSE: A simulation method is provided to reduce whole simulation time by successively processing additional simulations by using one simulator. CONSTITUTION: A verification software(32) executes first simulation process by adding an additional circuit or an additional code through an automation method. The verification software automatically collects minimum information from the first simulation process. The minimum information is necessary information for constructing simulation processes for one or more design blocks. The verification software rapidly executes the simulation processes by using the collected information.
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申请公布号 |
KR20120058991(A) |
申请公布日期 |
2012.06.08 |
申请号 |
KR20100120562 |
申请日期 |
2010.11.30 |
申请人 |
SYYTEM CENTROID INC.;YANG, SEI YANG |
发明人 |
YANG, SEI YANG |
分类号 |
G06F9/455;G06F11/30 |
主分类号 |
G06F9/455 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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