PROCESSOR WITH ADAPTIVE PIPELINE LENGTH

摘要

A system and method for reducing pipeline latency. In one embodiment, a processing system includes a processing pipeline. The processing pipeline includes a plurality of processing stages. Each stage is configured to further processing provided by a previous stage. A first of the stages is configured to perform a first function in a pipeline cycle. A second of the stages is disposed downstream of the first of the stages, and is configured to perform, in a pipeline cycle, a second function that is different from the first function. The first of the stages is further configured to selectably perform the first function and the second function in a pipeline cycle, and bypass the second of the stages.

主权项

1. A processor, comprising:
an execution pipeline comprising a plurality of stages; and pipeline control logic configured to:
identify an instruction being executed in the pipeline;determine whether the identified instruction can be processed by the pipeline using fewer than a total number of the pipeline stages; andselectably configure the pipeline to process the identified instruction using fewer than the total number of pipeline stages.