| 摘要 |
A sampling circuit module, a memory control circuit unit, and a method for sampling data are provided. The sampling circuit module includes a state machine circuit, a first delay line circuit, a second delay line circuit and a delay signal output circuit. In response to a first control signal, the state machine circuit outputs a second control signal and/or a third control signal. The first delay line circuit is configured to receive a reference clock signal and the second control signal to output a first delay clock signal. The second delay line circuit is configured to receive the reference clock signal and the third control signal to output a second delay clock signal. The delay signal output circuit is configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal. |
| 主权项 |
1. A sampling circuit module, comprising:
a delay-locked loop, comprising:
a control circuit, configured to receive a reference clock signal to output a first control signal; anda delay circuit, coupled to the control circuit and comprising:
a state machine circuit, configured to receive the first control signal and output a second control signal and/or a third control signal in response to the first control signal;a first delay line circuit, coupled to the state machine circuit and configured to receive the reference clock signal and the second control signal to output a first delay clock signal;a second delay line circuit, coupled to the state machine circuit and configured to receive the reference clock signal and the third control signal to output a second delay clock signal; anda delay signal output circuit, coupled to the first delay line circuit, the second delay line circuit and the state machine circuit and configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal; and a sampling circuit, coupled to the delay-locked loop and configured to receive the third delay clock signal and sample a data signal according to the third delay clock signal to obtain sampled data. |
