发明名称 |
Semiconductor device, semiconductor memory device and data processing system comprising semiconductor system |
摘要 |
A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line. |
申请公布号 |
USRE45819(E1) |
申请公布日期 |
2015.12.15 |
申请号 |
US201414302867 |
申请日期 |
2014.06.12 |
申请人 |
PS4 Luxco S.a.r.l. |
发明人 |
Kajigaya Kazuhiko |
分类号 |
G11C11/24;G11C7/06;G11C11/4091;G11C11/404 |
主分类号 |
G11C11/24 |
代理机构 |
Kunzler Law Group, PC |
代理人 |
Kunzler Law Group, PC |
主权项 |
1. A semiconductor device comprising:
a memory cell storing data; a bit line connected to the memory cell; a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, the sense amplifier receiving a signal voltage read out to the bit line in response to the data of the memory cell at a sense node connected to a gate of a transistor and amplifying a voltage at the sense node; a transfer control circuit including a transfer transistor controlling an electrical connection between the bit line and the sense node in response to a transfer control voltage inputted to a gate; and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage corresponding to data of high-level of the memory cell, wherein the third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line. |
地址 |
Luxembourg LU |