Memory controller with fast reacquisition of read timing to support rank switching

摘要

Techniques for performing fast timing reacquisition of read timing in a memory controller to support rank switching device are described. During operation, a memory controller receives read data for a read operation, wherein the read data includes a calibration preamble. The memory controller uses the calibration preamble to perform a fast timing reacquisition operation to compensate for a timing drift between a clock path and a data path for the read data. In particular, the memory controller performs the fast timing reacquisition by adjusting a data delay line coupled to a clock path associated with a control loop, wherein the control loop controls a data clock which is used to receive read data at the memory controller.

主权项

1. A method for performing a fast timing reacquisition in a memory controller, comprising:
during a read operation,
receiving, via a signal line, a data signal at the memory controller, wherein the data signal includes a timing reference signal followed by read data; andusing the timing reference signal included in the data signal to perform the fast timing reacquisition to compensate for a timing drift between a clock path and a data path for the read data;wherein performing the fast timing reacquisition comprises adjusting a data delay line coupled to the clock path and associated with a control loop, wherein the control loop controls a clock signal used to receive the data signal at the memory controller.