发明名称 |
Dual-port static random access memory (SRAM) |
摘要 |
In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit. |
申请公布号 |
US9208853(B2) |
申请公布日期 |
2015.12.08 |
申请号 |
US201313842086 |
申请日期 |
2013.03.15 |
申请人 |
Intel Corporation |
发明人 |
Kolar Pramod;Pandya Gunjan H.;Bhattacharya Uddalak;Guo Zheng |
分类号 |
G11C11/40;G11C11/412;G11C8/16 |
主分类号 |
G11C11/40 |
代理机构 |
Blakely, Sokoloff, Taylor & Zafman LLP |
代理人 |
Blakely, Sokoloff, Taylor & Zafman LLP |
主权项 |
1. A memory cell circuit for storing data, comprising:
a pair of cross-coupled inverters for storing states of the memory cell circuit; a plurality of access devices coupled to the pair of cross-coupled inverters, the plurality of access devices to provide access to the pair of cross-coupled inverters; and a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices coupled to the pair of cross-coupled inverters, the set of electrically inactive PMOS devices in combination with a portion of the pair of cross-coupled inverters to enable a continuous p-type diffusion layer for the memory cell circuit, wherein a gate of a first electrically inactive PMOS device is coupled to a gate of a second electrically inactive PMOS device, wherein the first electrically inactive PMOS device is coupled to an access device of the plurality of access devices. |
地址 |
Santa Clara CA US |